FIELD OF THE INVENTION
The present invention relates to a sense circuit for semiconductor memory devices, and more particularly to a sense circuit which is suitable for faster operations of MOS type dynamic random access memory (DRAM) integrated circuits.
Conventionally, in a DRAM, a cell for storing information is provided at each intersection between one pair of bit lines and a word line, and composed of an access transistor and a capacitor, wherein stored information is held as an amount of charges accumulated in the capacitor. With this configuration, to output the stored information held in the capacitor to the outside, the amount of charges must be amplified through a sense amplifier to generate a signal having a predetermined magnitude.
FIG. 1 shows a part of a peripheral circuit including a sense amplifier for a DRAM. A similar configuration is also shown, for example, in "1989 IEEE ISSCC", pp. 246-247. In FIG. 1, an NMOS (n-type MOS) access transistor 38 and a capacitor 39 constitute a memory cell. One terminal of the access transistor 38 is connected to a bit line (BL) 36.
A signal on the bit line 36 is transmitted to one input/output terminal (RL) 46 of a sense amplifier 48 through a switching element 43 formed of an NMOS transistor. On the other hand, an opposite bit line (BL) 37, which is not connected with the memory cell having the access transistor 38 turned on and connected to a word line (WL) 41 under consideration, supplies a reference voltage (normally Vcc/2) to the other input/ output terminal (RL) 47 of the sense amplifier 48 through a switching element 44. This reference voltage is supplied from a reference voltage line (VBLP) 31 through a transistor 35.
Charges accumulated in the capacitor 39 through the above-mentioned configuration are amplified by the sense amplifier 48. An output signal of the sense amplifier 48 is transmitted to external output lines (DL, DL) 53, 54 through NMOS transistors 51, 52 which are turned on by a selection signal (COL) 50 generated by a column address signal for the memory.
Transistors 33, 34, 35 in the circuit are turned on by an equalization signal (PEQ) 32 to couple a reference signal line (VBLP) 31 to the pair of bit lines (BL, BL) 36, 37 for equalizing the potentials on the respective bit lines.
FIG. 2 shows an example of a circuit configuration typically used in the sense amplifier circuit 48. In this circuit, sense amplifier activation signals (SP, SN) 45, 49 turn on transistors 60, 65 held at a power supply potential and, a ground potential, respectively, to cause the sense amplifier to initiate its operation, so that amplified signals are delivered to input/output lines (input/output terminals) 46, 47, respectively. Each of the amplified signals has a polarity in accordance with a difference between potentials appearing on the input/output lines (input/output terminals) (RL, RL) 46, 47 on which signals are transmitted from the bit lines 36, 37. The input/output lines (input/output terminals) 46, 47 of the sense amplifier are also referred to as "read-out line(s)" in the following description.
A scheme using the above-mentioned sense amplifier is referred to as a latch type sensing scheme which has been widely employed in DRAMs. A latch circuit composed of PMOS (p-type MOS) transistors 61, 62 and NMOS transistors 63, 64 is essentially a flip-flop circuit similar to an SRAM cell. Since the operation of such a latch circuit is well known in the art, explanation thereof is omitted. Reference numerals 59, 66 designate terminals which provide a supply voltage Vcc and a ground voltage, respectively.
A read-out operation based on the configuration described above may be conceptually represented by waveform charts of FIG. 3. It is assumed that one terminal of the capacitor 39 is connected to a terminal (VCP) 40, and the capacitor 39 accumulates charges at the level of the power supply potential Vcc (5 volts). Assume also that the ground potential is, for example, zero volts, and the reference voltage is 2.5 volts. In an initial state, since an equalization signal (PEQ) 32 is at five volts, the NMOS transistors 33, 34, 35 are turned on to cause the reference signal at 2.5 volts to be supplied from the reference signal line 31 to the bit lines 36, 37.
When the equalization signal 32 falls from five volts to zero volts in synchronism with a RAS signal (not shown), and then the word line 41 is selected so that the voltage thereon rises from zero volts to approximately 7.5 volts, the access transistor 38 is turned on to cause charges accumulated in the capacitor 39 to appear on the bit line 36. This results in the potential on the bit line 36 rising a little more than 2.5 volts. On the other hand, the potential on the bit line 37, presenting few changes, is held at 2.5 volts.
When a small difference between the potentials on these bit lines 36, 37 increases to approximately 300 millivolts with the voltage on the word line 41 being in a raised state, a bit line switching signal (SE) 42 changes from zero volts to five volts to cause the switching transistors 43, 44 to turn on.
After the signals on the bit lines 36, 37 have been transmitted to the input/output lines of the sense amplifier 48 through the transistors 43, 44, the sense amplifier activation signals 45, 49 changed to zero volts and five volts, respectively, allowing the sense amplifier to operate, with the result that the difference between the potentials on the bit lines 36, 37 as well as the difference between the potentials on the read-out lines (input/output lines of the sense amplifier 48) 46, 47 begin to increase.
At the time the difference between the potentials on the read-out lines 46, 47 further increases, a selection signal 50 supplies a pulse having an amplitude of five volts. This causes the NMOS transistors 51, 52 to turn on only for a duration of the pulse width so that the small potential difference appears between the external output lines 53, 54 for that period. This signal is typically received and amplified by a current mirror type sense amplifier having a higher sensitivity, and outputted to the outside.
When the pulse is supplied onto the selection signal line 50, the external output lines 53, 54 act as large loads, viewed from the sense amplifier 48, so that the potential differences between signals on the read-out lines 46, 47 and between signals on the bit lines 36, 37 are reduced. When the pulse is ended, however, the potential differences again increase.
Subsequently, an amount of charges corresponding to stored information must be re-stored into the memory cell. For this purpose, the sense amplifier 48 is driven to provide five volts to the read-out line 46 and the bit line 36 as well as zero volts to the read-out line 47 and the bit line 37. The potential on the word line 41 is decreased from 7.5 volts to zero volts when the re-storage is completed.
Then, after peripheral control signals of the sense amplifier 48 are made inactive the voltage of the equalization signal 32 is raised, and the bit lines 36, 37 are equalized to complete the read-out operation.
However, when the prior art example as described above is used in a DRAM, problems may arise as follows. Specifically, a bit line capacitance parasitic on the bit line is typically large and approximately ten times more than the capacitance of a capacitor included in a memory cell. Also, due to the configuration of the sense amplifier, a gate capacitance and a bonding capacitance of the sense amplifier itself also act as non-negligible loads.
Therefore, when an amount of charges accumulated in a capacitor is amplified by the sense amplifier 48 or when re-storage is performed, a self load of the sense amplifier, and parasitic capacitances on a bit line and a read-out line, on which read charges are transmitted, are regarded as a load, viewed from the sense amplifier. Particularly, this increase in load tends to extend a delay time required to re-store information into memory cells.